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synchronous ethernet frequency translator ICS840271I idt? / ics? syn chronous ethernet frequency translator 1 ics840271bgi rev. a april 23, 2009 general description the ICS840271I is a pll-based frequency translator intended for use in telecommunication applications such as synchronous ethernet. the internal pll translates ethernet clock frequencies such as 125mhz (1gb ethernet), 156.25mhz (10gbe xaui) and 161.1328mhz ( 10gb ethernet) to an output frequency of 25mhz. the pll does not any require external components. the input frequency is selectable by a 2-pin interface. the ICS840271I is opti mized for low cycle-to-cycle jitter on the 25mhz output signal. the input of the device accepts differential (lvpecl, lvds, lvhstl, sstl, hcsl) or single-ended (lvcmos) signals. the extended temperature range supports telecommunication and networking equipment requirements. the ICS840271I us es a small rohs 6, 8-pin tssop package and is an effective solution for space-constrained applications. features ? clock frequency translator for synchronous ethernet applications ? one single-ended output (lvcmos or lvttl levels), 16 ? output impedance ? differential input pair (clk, nclk) accepts lvpecl, lvds, lvhstl, sstl, hcsl input levels ? supports input clock frequencies of: 125mhz, 156.25mhz or 161.1328mhz ? generates a 25mhz output clock signal ? internal resistor bias on nclk pin allows the user to drive clk input with external single-ended (lvcmos/lvttl) input levels ? internal pll is optimized for low cycle-to-cycle jitter at the output ? full 3.3v or 2.5v supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package hiperclocks? ic s ICS840271I 8 lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view pin assignment 1 2 3 4 8 7 6 5 v dda nclk clk sel0 gnd q sel1 v dd 25 mhz q sel(1:0) input control logic clk nclk 00 = pll bypass 01 = 161.1328125 mhz 10 = 156.2500000 mhz 11 = 125.0000000 mhz pll pre- divider output divider feedback divider block diagram
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 2 ics840271bgi rev. a april 23, 2009 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3. sel[1:0] function table note: ref = input clock signal frequency number name type description 1v dda power analog supply pin. 2 sel0 input pulldown selects the input reference fre quency and the pll bypass mode. lvcmos/lvttl interface levels. see table 3. 3 clk input pulldown non-inverting differential clock input. 4 nclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v dd /2. 5 sel1 input pullup selects the input reference fre quency and the pll bypass mode. lvcmos/lvttl interface levels. see table 3. 6 gnd power power supply ground. 7 q output single-ended clock output. lv cmos/lvttl interface levels. 8v dd power core supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v dd = 3.465v 16 ? v dd = 2.625v 19 ? inputs mode output (mhz) sel1 sel0 clk, nclk (mhz) 0 0 ref pll bypass ref/ 5 0 1 161.1328125 pll enabled 25 1 (default) 0 (default) 156.25 pll enabled 25 1 1 125 pll enabled 25
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 3 ics840271bgi rev. a april 23, 2009 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 2.5v5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvcmos) -0.5v to v dd + 0.5v package thermal impedance, ja 129.5c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.08 3.3 v dd v i dd power supply current 75 ma i dda analog supply current 8ma symbol parameter test conditions minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd ? 0.08 2.5 v dd v i dd power supply current 72 ma i dda analog supply current 8ma
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 4 ics840271bgi rev. a april 23, 2009 table 4c. lvcmos/lvttl dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c table 4d. differential dc characteristics, v dd = 3.3v5% or 2.5v5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current sel1 v dd = v in = 3.465v or 2.625v 5 a sel0 v dd = v in = 3.465v or 2.625v 150 a i il input low current sel1 v dd = 3.465v, v in = 0v -150 a sel0 v dd = 3.465v, v in = 0v -5 a v oh output high voltage v dd = 3.465v, i oh = 12ma 2.6 v v dd = 2.625v, i oh = 12ma 1.8 v v ol output low voltage v dd = 3.465v or 2.625v, i ol = -12ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk/nclk v dd = v in = 3.465v or 2.625v 150 a i il input low current clk v dd = 3.465v or 2.625v, v in = 0v -5 a nclk v dd = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 5 ics840271bgi rev. a april 23, 2009 ac electrical characteristics table 5a. ac characteristics, v dd = 3.3v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. table 5b. ac characteristics, v dd = 2.5v5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f out output frequency 25 mhz t jit(cc)) cycle-to-cycle jitter sel0 sel1 40 ps sel0 = sel1 = 1 15 ps t lock pll lock time sel1 = 0, sel0 = 1 1 s sel 1 = 1, sel0 = x 50 ms t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 % symbol parameter test conditions minimum typical maximum units f out output frequency 25 mhz t jit(cc)) cycle-to-cycle jitter sel0 sel1 50 ps sel0 = sel1 = 1 15 ps t lock pll lock time sel1 = 0, sel0 = 1 1 s sel 1 = 1, sel0 = x 50 ms t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle 47 53 %
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 6 ics840271bgi rev. a april 23, 2009 parameter measureme nt information 3.3v output load ac test circuit differential input level output duty cycle/pulse width/period 2.5v output load ac test circuit cycle-to-cycle jitter output rise/fall time scope qx lvcmos gnd -1.65v5% 1.65v5% v dd v dda 1.65v5% nclk clk v dd gnd v cmr cross points v pp t period t pw t period odc = v ddo 2 x 100% t pw q scope qx lvcmos gnd -1.25v5% 1.25v5% v dd v dda 1.25v5% ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles q 20% 80% 80% 20% t r t f q
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 7 ics840271bgi rev. a april 23, 2009 application information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform- ance, power supply isolation is required. the ICS840271I provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individual- ly connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ended signal driving differential input recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. v dd v dda 3.3v or 2.5v 10 ? 10f .01f .01f v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 8 ics840271bgi rev. a april 23, 2009 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. bo th signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 3b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 3f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 9 ics840271bgi rev. a april 23, 2009 schematic example figure 4 shows an example of ICS840271I applications schematic. in this example, the device is operated at v dd = 3.3v. the input is driven by either a 3.3v lvpecl or lvds driver. one example of lvcmos termination is shown in this schematic. the decoupling capacitors should be located a close as possible to the power pin. figure 4. ICS840271I schematic layout vdd u1 1 2 3 4 8 7 6 5 vdda sel0 clk nclk vdd q gnd sel1 nclk r3 125 vdd sel1 r1 10 logic input pin examples rd1 not install q ru2 not install c3 10u r2 33 set logic input to '1' set logic input to '0' vdda vdd zo = 50 r4 125 lvpecl driv er c2 0.1u zo = 50 clk c1 0.01u r6 84 r5 84 lvcmos vdd ru1 1k to logic input pins vdd sel0 rd2 1k to logic input pins zo = 50 ohm
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 10 ics840271bgi rev. a april 23, 2009 power considerations this section provides information on power dissipation and junction temperature for the ICS840271I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS840271I is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd + i dda ) = 3.465v *(75ma + 8ma) = 287.6mw output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 16 ? )] = 26.25ma power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 16 ? * (26.25ma) 2 = 11mw per output total power dissipation total power = power (core) max + total power (r out ) = 287.6mw + 11mw = 298.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 129.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.299w *129.5c/w = 123.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 8 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 1 25.5c/w 123.5c/w
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 11 ics840271bgi rev. a april 23, 2009 reliability information table 7. ja vs. air flow table for a 8 lead tssop transistor count the transistor count for ICS840271I is: 2732 package outline and package dimensions package outline - g suffix for 8 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 1 25.5c/w 123.5c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS840271I synchronous ethernet frequency translator idt? / ics? syn chronous ethernet frequency translator 12 ics840271bgi rev. a april 23, 2009 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 840271bgilf 71bil ?lead-free? 8 lead tssop tube -40 c to 85 c 840271bgilft 71bil ?lead-free? 8 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
ICS840271I synchronous ethernet frequency translator www.idt.com ? 2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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